Embodiments of the present invention relate to a vertical semiconductor device, and more particularly to a vertical semiconductor device for effectively removing a floating body effect, a module and system each including the same, and a method for manufacturing the vertical semiconductor device.
With the increasing integration degree of semiconductor devices, the demand of DRAM devices of 40 nm or less is rapidly increasing. However, it is very difficult to reduce a unit cell size of a transistor in 8F2 (F: minimum feature size) or 6F2 cell structure down to 40 nm or less. Therefore, a DRAM device having a 4F2 cell structure has been developed to increase integration by about 1.5˜2 times.
In order to construct the 4F2 cell structure, a source unit and a drain unit of a cell transistor may be formed in a 1F2-sized region. For this purpose, many companies are conducting intensive research into a vertical-type cell transistor structure in which the source unit and the drain unit can be formed within the 1F2-sized region. The vertical-type cell transistor configures a channel of a transistor for operating the cell in the form of a pillar, and includes a source region and a drain region in an upper part and a lower part, respectively.
However, a bit line junction region of the 4F2 cell structure is formed as an One Side Contact (OSC) at a lateral surface of a lower part of the pillar.
Therefore, if the bit line junction region is formed to have a shallow junction depth, a region where a gate overlaps with the junction region is narrow, such that channel resistance is increased and a threshold voltage is increased. On the other hand, if the bit line junction region is formed to have a deep junction depth, such that there is an increased area of overlap between the gate and the junction region, a pillar is isolated from the underlying substrate, so that a floating body effect arises.